18. Cache Test Mode

18.4 Exit Sequence

To leave cache test mode, the external agent does the following:

loads the mode bits into the processor by driving the mode bits (with the CTM mode bit negated) on SysAD(63:0)
waits at least two SysClk cycles
asserts SysGnt* for at least one SysClk cycle

After at least one SysClk cycle, the external agent may negate SysReset* to end the reset sequence.

Figure 18-2 shows the cache test mode exit sequence.

Figure 18-2 Cache Test Mode Exit Sequence

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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